What is the difference between RISC and CISC machines? Write some points about advantages and disadvantages of CISC machine.
The instruction set of a computer specifies the primitive commands or machine instructions that a programmer can use in programming the machine. The complexity of an instruction set is attributed to the instruction format, data format, addressing modes, general purpose registers, opcode specifications and flow control mechanisms used. The difference between CISC and RISC machines are listed below:
Architectural characteristics | CISC | RISC |
Instruction set size and instruction format | Large set of instruction variable formats (16-64 bits/inst) | Small set of instruction with fixed (32 bit) format and most register based instruction |
Addressing modes | 12-24 | 3-5 |
General purpose register and cache design | 8-24 GPRs , mostly with unified cache | 32-192 GPRs, with split cache(data and instruction) |
Clock rate and CPI | 33-50 MHzCPI 2-15 | 50-150MHzCPI <1.5 |
CPU control | Microprogrammed control unit | Hardwired control unit |
Fig: CISC architecture with unified cache
Fig: RISC architecture with split cache
Reduced Instruction Set Computer(RISC):
Key features:
- large number of general purpose register used
- use of compiler technology to optimize register use
- limited and simple instruction set
- emphasis on optimizing the instruction pipeline
Characteristics:
- one instruction per cycle
- register to register operations
- few, simple addressing modes
- few, simple instruction formats
- hardwired design (no microcode)
- fixed instruction format
- more compile time/effort
Complex Instruction Set Computer (CISC):
Characteristics:
- to attempt to provide a single machine instruction for each statement that is written in a high level language
- variable length instruction format
- provides direct manipulation of operands residing in memory
- a large number of instruction typically from 100 to 250
- some instructions that perform specialized tasks and are used frequently
- a large variety of addressing modes typically from 5 to 20